About video-cores.com

Development Process

Creating an industry-standard core is a process that starts with the reading of the official standard and discussing among the team any questions regarding interpretation. When needed, one of many industry expert advisors are consulted on specific interpretation details. Real-life usage cases and extra tolerances are added to make sure that the video cores will interface with other cores or chips.  video-cores.com only develops interfaces or video processing blocks in which at least one of the team members has been a very experienced industry user.

Cores that don't follow standards are created to provide the smallest and fastest design that provides the image or sound quality that the customer approves.

A core test plan identifies all normal-usage and corner cases and defines a detailed set of directed and pseudo-random tests to run.

Each core is written in close consultation with the IEEE 1364-2001 Verilog standard and cross-checked with multiple simulation, code checking and synthesis tools.

The core is complete when it passes a regression that includes measurements for functional coverage, code coverage and code checking guidelines.

Clients

All of our clients request and receive confidentiality on who they are.  We can share Markets where our products are currently used:

  • Broadcast Video and Audio
  • Prosumer CCD Cameras
  • Consumer Electronics
  • Industrial Vision

Business

video-cores.com is the product division of PugMedia Inc., a profitable United States of America "C" Corporation.  This division was started in March of 2005 and shortly thereafter started licensing cores to customers.

All cores are Architected, Designed and Verified in the United States of America.

Raul I. Lopez

Raul brings more than 15 years of experience in the semiconductor industry to his position as General Manager and Lead Core Developer of video-cores.com. His background of product-oriented video management, design and verification experience includes:

  • Stanford University (Boltzmann Neural Network chip, full-custom memory design)
  • C-Cube Microsystems (MPEG-2 encoders: CL4010/20/30 DVxpertTM, verification and final image quality)
  • IZAHI (MPEG-2 post-processor: IZx, design and production)
  • Silicon Graphics (Uncompressed SD/HD I/O: DMediaPro® DM3, HD GVO, managed HW engineering team)
  • TeraLogic / Oak Technology / Zoran (DTV SoCs: Generation9TM, Generation9-Elite, SupraHDTM, verified two chip generations and re-designed video capture).

Raul received a BSEE from ITESO University in Guadalajara, Mexico, and MSEE and EngEE graduate degrees from Stanford University specializing in Computer Architecture and Microprocessor Design.